# R&D Engineering, Sr Engineer

**Company**: Synopsys
**Location**: Seongnam-si, Gyeonggi-do
**Experience**: senior
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology
**Ticker**: SNPS
**Wikidata**: https://www.wikidata.org/wiki/Q2303478

**Apply**: https://careers.synopsys.com/job/seongnam-si/r-and-d-engineering-sr-engineer/44408/102756615296?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_10520d92-fbb

## Description

Synopsys software engineers are key enablers in the world of Electronic Design Automation (EDA), developing and maintaining software used in chip design, verification and manufacturing. They work on assignments like designing, developing, and troubleshooting software, leveraging the state-of-the-art technologies like AI/ML, GenAI and Cloud.

As a Senior Engineer in R&D Engineering, you will work directly with foundry partners and advanced node enablement teams on designs that define what is possible at the next process node.

**Responsibilities**

- Develop and optimize foundry implementation and 3DIC solutions using Synopsys Fusion Compiler, aligned with reference methodology and advanced node requirements

- Provide direct engineering support to foundry partners and end customers on DTCO, PPA optimization, and test chip bring-up for cutting-edge process nodes

- Debug complex place and route, timing, power, and physical verification issues across multi-corner, multi-mode designs using tools like PrimeTime, StarRC, IC Validator, and RedHawk

- Drive foundry test chip projects from RTL to GDS, coordinating with Synopsys advanced node enablement teams and foundry process groups

- Work with field account teams and internal jumpstart teams to support mutual customer engagements and accelerate adoption of Synopsys physical design solutions

- Collaborate with cross-functional engineering teams across geographies to resolve real project issues, improve implementation flows, and close PPA gaps

- Explore and integrate productivity improvements using modern engineering tools and AI-assisted solutions like Cursor to accelerate design and debug cycles

**The Impact You Will Have**

- Enable successful tape-outs at advanced nodes by delivering optimized physical design solutions that meet aggressive PPA targets

- Accelerate foundry partner readiness and customer adoption of next-generation process technologies through hands-on implementation support and flow development

- Improve design quality and reduce iteration cycles by identifying and resolving complex timing, power, and signoff issues before they reach customers

- Influence foundry roadmap decisions and design rule development by providing real-world feedback from test chip implementation and customer engagements

- Build reusable methodologies and automation that scale across multiple projects, reducing bring-up time for future advanced node designs

- Strengthen customer relationships and drive tool adoption by solving critical design challenges that directly impact their product schedules

- Contribute to the continuous improvement of Synopsys physical design tools and flows based on frontline experience with the hardest implementation problems

**Requirements**

- Bachelor's or Master's degree in Electrical Engineering with 2+ years of hands-on experience in physical design implementation

- Proficiency in place and route methodology, hierarchical design, and timing signoff using Synopsys Fusion Compiler or equivalent P&R tools

- Hands-on experience with physical design signoff tools such as PrimeTime for timing, StarRC for extraction, IC Validator for DRC/LVS, or RedHawk for power analysis

- Demonstrated ability to debug complex implementation issues across multiple domains including timing closure, power integrity, and physical verification

- Experience working on high-performance or low-power designs with a track record of contributing to PPA improvements and flow optimization

- Real tape-out experience on SoC, CPU, or GPU projects is a strong plus

- Exposure to AI-assisted engineering tools like Cursor or similar automation frameworks is a plus

**Benefits**

- Comprehensive medical and healthcare plans that work for you and your family

- Time away: company holidays, ETO and FTO Programs

- Family support: maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more

- ESPP: purchase Synopsys common stock at a 15% discount, with a 24-month look-back

- Retirement plans: save for your future with our retirement plans that vary by region and country

- Competitive salaries

## Skills

### Required
- Electrical Engineering
- physical design implementation
- Synopsys Fusion Compiler
- PrimeTime
- StarRC
- IC Validator
- RedHawk

### Nice to have
- AI-assisted engineering tools like Cursor
- automation frameworks
- SoC
- CPU
- GPU

---

Source: [Apply at careers.synopsys.com](https://careers.synopsys.com/job/seongnam-si/r-and-d-engineering-sr-engineer/44408/102756615296?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)