# Sr. Staff Digital Verification Engineer (Memory Interface IP- HBM/DDR/LPDDR)

**Company**: Synopsys
**Location**: Hyderabad, Telangana
**Work arrangement**: onsite
**Experience**: senior
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology
**Ticker**: SNPS
**Wikidata**: https://www.wikidata.org/wiki/Q2303478

**Apply**: https://careers.synopsys.com/job/hyderabad/sr-staff-digital-verification-engineer-memory-interface-ip-hbm-ddr-lpddr/44408/100624924064?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_101fec81-0a9

## Description

You will be a Sr. Staff Digital Verification Engineer at Synopsys, working on Memory Interface IP, specifically HBM, DDR, and LPDDR.

You have spent over a decade verifying complex ASIC designs and have extensive experience with memory interfaces, including their ecosystems, timing constraints, power states, and failure modes.

Your responsibilities will include:

- Designing and building verification environments for Interface IP protocols using SystemVerilog and UVM

- Writing detailed test plans covering functional scenarios, corner cases, and protocol compliance

- Developing reusable verification IP and testbenches adaptable across multiple projects and IP variants

- Collaborating with design and architecture teams to identify bugs and close coverage gaps

- Running functional coverage analysis and driving coverage closure

- Mentoring junior verification engineers on UVM best practices and verification strategies

- Using simulation tools like VCS or ModelSim to execute regression suites and validate design changes

You will have the opportunity to deliver Interface IP that powers memory subsystems in AI accelerators, mobile SoCs, and high-performance computing platforms, reducing post-silicon bugs and customer escalations.

The ideal candidate has 6-8+ years of hands-on ASIC or SoC verification experience, a proven track record verifying Interface IP protocols, and strong proficiency in SystemVerilog and UVM.

Benefits include comprehensive medical and healthcare plans, time away programs, family support, ESPP, retirement plans, and competitive salaries.

## Skills

### Required
- SystemVerilog
- UVM
- ASIC verification
- SoC verification
- Interface IP protocols
- HBM
- DDR
- LPDDR
- AMBA

### Nice to have
- HBM2
- HBM3
- DDR4
- DDR5
- LPDDR4
- LPDDR5

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Source: [Apply at careers.synopsys.com](https://careers.synopsys.com/job/hyderabad/sr-staff-digital-verification-engineer-memory-interface-ip-hbm-ddr-lpddr/44408/100624924064?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)