# ASIC Implementation Technical Lead

**Company**: Cisco
**Location**: Vancouver, British Columbia
**Experience**: senior
**Job type**: full-time
**Salary**: $147,400.00 to $198,200.00
**Category**: Engineering
**Industry**: Technology

**Apply**: https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/Vancouver-British-Columbia-Canada/ASIC-Development-Technical-Leader_2028205?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/job/asic-implementation-technical-lead-0ec3586c-0aa/

## Description

The Silicon One team at Cisco is looking for an ASIC Implementation Technical Lead with a primary focus on Design-for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle. As a member of this team, you will also be involved in crafting groundbreaking next-generation networking chips.

Responsibilities:

- Work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle

- Help lead to drive the DFT and quality process through the entire Implementation flow and post silicon validation phases with additional exposure to physical design signoff activities

Minimum Qualifications:

- Bachelor’s degree in Electrical or Computer engineering and 8+ years of ASIC Design experience, or Master’s degree in Electrical Engineering or Computer Engineering and 6+ years of ASIC Design experience, or PhD in Electrical Engineering or Computer Engineering + 3 years of ASIC Design experience

- Prior experience with scan insertion

- Prior experience with ATPG and EDA tools like Tessent tool sets

- Prior experience working with Gate level simulation, including timing-based simulations with Standard Delay Format (SDF), debugging with VCS and other simulators

- Post-silicon validation and debug experience; Ability to work with ATE engineers on pattern translation and validation

Preferred Qualifications:

- Verilog design experience – developing custom DFT logic & IP integration; familiarity with functional verification

- Prior experience with Jtag protocols (p1500, p1687)

- Scripting skills: Tcl, Python/Perl

- Prior experience with test static timing analysis constraints development and timing closure

- Prior experience with SSN

Benefits:

- Medical, dental and vision insurance

- 401(k) plan with a Cisco matching contribution

- Paid parental leave

- Short and long-term disability coverage

- Basic life insurance

- Paid time away

- Optional 10 paid days per full calendar year to volunteer

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## Skills

### Required
- ASIC Design
- DFT
- Scan Insertion
- ATPG
- Tessent tool sets
- Gate level simulation
- Standard Delay Format (SDF)
- VCS
- Post-silicon validation
- ATE engineers

### Nice to have
- Verilog design
- Jtag protocols
- Tcl
- Python/Perl
- Test static timing analysis
- SSN

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Source: [Apply at cisco.wd5.myworkdayjobs.com](https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/Vancouver-British-Columbia-Canada/ASIC-Development-Technical-Leader_2028205?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)