# DFT, Principal Engineer **Company**: Synopsys **Location**: Austin, Texas **Work arrangement**: onsite **Experience**: senior **Job type**: full-time **Salary**: $170000-$255000 **Category**: Engineering **Industry**: Technology **Ticker**: SNPS **Wikidata**: https://www.wikidata.org/wiki/Q2303478 **Apply**: https://careers.synopsys.com/job/austin/dft-principal-engineer/44408/101617800704?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply **Canonical**: https://yubhub.co/jobs/job_0e0851a9-6ad ## Description Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. You are a hands-on DFT expert who has driven test architecture and implementation for complex SoCs that tape out and succeed in production, not just in reviews. You understand how decisions made around RTL freeze impact coverage, yield, and test cost at volume, and you can confidently define the right strategy across scan/ATPG, MBIST/LBIST, and broader test hooks needed for bring-up and failure analysis. **Responsibilities** - Own DFT architecture, implementation, integration, and verification for complex SoCs and subsystems from specification through tapeout, working directly with customer and internal design teams - Define and execute test strategies across scan insertion and ATPG, memory BIST, logic BIST, and analog/PHY test considerations to meet coverage, quality, yield, and cost targets - Drive DFT signoff readiness by identifying testability risks early, proposing design changes, and ensuring closure across the RTL-to-GDS flow - Develop and institutionalize reusable DFT methodologies, checklists, and guidelines using Synopsys EDA tools to solve real customer problems on active service projects - Partner with silicon validation and test engineering teams on post-silicon debug, failure analysis triage, and pattern refinement to improve production outcomes - Collaborate closely with RTL design, functional verification, physical design, timing, and power teams to ensure testability is designed in from architecture through signoff - Provide technical guidance to peers through design reviews, integration/debug support, and best-practice sharing **The Impact You Will Have** - Enable first-pass silicon success by surfacing and resolving DFT issues before tapeout - Improve test coverage and yield through robust scan/ATPG and BIST strategies aligned to product constraints - Reduce production test time and cost for SoCs in high-performance computing, automotive, and aerospace domains - Create reusable DFT methodologies that scale across multiple programs and customer engagements - Strengthen customer confidence by delivering DFT solutions that work in production, not just in simulation - Influence Synopsys tools and IP direction by feeding back real project learnings and customer pain points - Accelerate tapeout schedules by catching testability gaps early and proposing fixes teams can implement without rework **Requirements** - Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, or related field - Typically 10+ years of hands-on SoC DFT experience with proven depth in scan/ATPG, memory BIST, logic BIST, and analog test considerations - Strong understanding of the end-to-end SoC design flow from microarchitecture through RTL, verification, synthesis, timing/physical implementation, and signoff - Demonstrated experience owning DFT implementation for complex SoCs that have taped out and gone to production - Strong working knowledge of Synopsys DFT tools such as TetraMAX, DFT Compiler, and BIST Architect is a plus - Proven ability to work cross-functionally to resolve testability issues and drive closure under schedule constraints - Post-silicon debug experience and collaboration with test engineering teams to refine production test programs is a plus **Benefits** - Comprehensive medical and healthcare plans that work for you and your family - In addition to company holidays, we have ETO and FTO Programs - Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more - Purchase Synopsys common stock at a 15% discount, with a 24-month look-back - Save for your future with our retirement plans that vary by region and country - Competitive salaries ## Skills ### Required - DFT - SoC - scan/ATPG - memory BIST - logic BIST - analog test considerations - Synopsys DFT tools ### Nice to have - post-silicon debug - collaboration with test engineering teams --- Source: [Apply at careers.synopsys.com](https://careers.synopsys.com/job/austin/dft-principal-engineer/44408/101617800704?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)