# ArchDesign Co-Design Engineer(NCG)

**Company**: NVIDIA
**Location**: Shanghai
**Experience**: senior
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology

**Apply**: https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/China-Shanghai/SCG-ArchDesign-Engineer---New-College-Grad-2027_JR2028968?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_0de0f73d-57c

## Description

We are seeking an ArchDesign Co-Design Engineer(NCG) to join our Silicon Co-Design Group (SCG) team at NVIDIA. As a member of this team, you will work at the intersection of design, architecture, marketing, operations, and productization. Your primary focus will be on silicon co-design through prototyping and design of experiments.

**Key Responsibilities:**

- Design and develop silicon co-design prototypes and measurement setups to analyze power-rail noise, circuit margin, performance, and binning behavior.

- Plan and execute design of experiments (DOE) to characterize and optimize silicon behavior.

- Build Python pipelines and analyses to turn prototype, DOE, simulation, and characterization data into actionable insights and inputs for firmware tuning, product specs, and manufacturing limits.

- Collaborate with cross-functional teams, including architecture, design, validation, and firmware, to ensure seamless integration and iteration of the prototype.

- Utilize secure, traceable, and validated AI-assisted workflows for experiment planning, analysis, and documentation.

**Requirements:**

- Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.

- At least 2 years of experience in a related silicon, validation, characterization, productization, or engineering-tools role.

- Working knowledge of silicon speed/power/quality concepts, such as DVFS, Vmin/Fmax, shmoo, PDN/noise, binning, or guardband.

- Hands-on experience with lab or post-silicon bring-up, experiment or characterization campaigns, manufacturing test/limits, or tools/pipelines that consume chip data.

- Proficiency in Python (or similar) for data analysis, automation, and validation; comfort with Git and structured test/regression.

**Nice to Have:**

- Experience running a test-chip, prototype vehicle, or characterization DOE.

- Direct experience on GPU/SoC/CPU power, performance, binning, PDN/noise, or sim-to-silicon correlation.

- Shipped an internal tool, dashboard, or data pipeline (Python, databases, web apps) that other people use.

- Hands-on experience with large language models (LLMs) in an engineering workflow.

NVIDIA offers competitive salaries and a generous benefits package.

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## Skills

### Required
- Electrical Engineering
- Computer Engineering
- Computer Science
- Python
- Git
- SQL
- data analysis
- automation
- validation

### Nice to have
- GPU/SoC/CPU power
- performance
- binning
- PDN/noise
- sim-to-silicon correlation
- large language models (LLMs)

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Source: [Apply at nvidia.wd5.myworkdayjobs.com](https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/China-Shanghai/SCG-ArchDesign-Engineer---New-College-Grad-2027_JR2028968?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)