# ASIC Failure Analysis Engineer (Hybrid)

**Company**: Cisco
**Location**: San Jose, California
**Work arrangement**: hybrid
**Experience**: senior
**Job type**: full-time
**Salary**: $167,700.00 - $245,200.00
**Category**: Engineering
**Industry**: Technology

**Apply**: https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/San-Jose-California-US/ASIC-Failure-Analysis-Engineer--Hybrid-_2027288?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_0de04e37-0c4

## Description

As a Failure Analysis Engineer, you will be part of the Quality and Reliability group, performing failure analysis of ASIC products.

This role will require a high level of collaboration and interaction with Product Test Engineering, Design Engineering, Quality Engineering, Assembly Engineering, and Foundry Engineering teams.

Responsibilities include:

- Conduct root cause failure analysis of silicon product reliability test and field failures and propose corrective actions.

- Develop and implement standard processes for failure analysis using all types of FA equipment.

- Coordinate all the logistics and instructions to direct the failure analysis process and carry out FA function in a systematic way.

- Document and report failure analysis results to management.

- Function as a technical resource for failure analysis questions.

- Develop and maintain relationships with FA service and equipment vendors.

- Interface with product, test, and design engineering groups to identify and characterize faults on emerging technologies, while providing fault isolation, identification, and characterization for yield/reliability failures.

Minimum Qualifications:

- Bachelor's degree in Electrical/Electronics Engineering or related required. Master's degree preferred.

- 8+ years of experience in semiconductor failure analysis field.

- Previous background writing and executing FA plans and interpret results from FA techniques such as cross-section, X-ray, CSAM, TDR, FIB, SEM, and TEM, IR/EMMI/OBIRCH.

- Validated ability to specify hardware and implement set up for dynamic FA using SIL (Solid Immersion Lens) and LSM (Laser Scanning Microscopy).

- Prior experience of fault isolation techniques using ATE, Scan/ATPG, MBIST to identify, isolate, and characterize device-level faults.

Preferred Qualifications:

- Semiconductor technology and process knowledge (Fab, Assembly, and Advanced Packaging).

- Good understanding of transistor function/basic electronics, semiconductor device physics, and behavior under various operating conditions.

- Proficient in ATE docked dynamic fault isolation using LVP, LVI/SMI, LADA, TIVA techniques.

- Knowledge of JEDEC IC Qualification tests and requirements is beneficial.

- Applied experience driving physical failure analysis with suppliers.

The starting salary range posted for this position is $167,700.00 to $245,200.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation, equity, or benefits.

## Skills

### Required
- Electrical/Electronics Engineering
- semiconductor failure analysis
- FA equipment
- SIL
- LSM
- ATE
- Scan/ATPG
- MBIST

### Nice to have
- Semiconductor technology
- transistor function
- basic electronics
- semiconductor device physics
- LVP
- LVI/SMI
- LADA
- TIVA
- JEDEC IC Qualification tests

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Source: [Apply at cisco.wd5.myworkdayjobs.com](https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/San-Jose-California-US/ASIC-Failure-Analysis-Engineer--Hybrid-_2027288?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)