# Analog Design - Staff Engineer **Company**: Synopsys **Location**: Bengaluru, Karnataka **Experience**: staff **Job type**: employee **Category**: Engineering **Industry**: Technology **Ticker**: SNPS **Wikidata**: https://www.wikidata.org/wiki/Q2303478 **Apply**: https://careers.synopsys.com/job/bengaluru/analog-design-staff-engineer/44408/97550666512?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply **Canonical**: https://yubhub.co/jobs/job_0cfff79a-28c ## Description Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. You have spent years in the trenches of analog design, working on circuits that move data at speeds most people cannot fathom. SerDes is not just a buzzword to you, it is the domain where you have built voltage-mode drivers, tuned PLLs until they locked cleanly, and debugged equalization schemes that looked perfect in simulation but needed three more iterations in layout. You know that a well-designed CDR is the difference between a link that works and one that fails margin at the customer site. At Synopsys, you will work on SerDes IP that ships in AI accelerators, data center switches, automotive SoCs, and consumer electronics. The circuits you design will be measured in gigabits per second, and the decisions you make will matter in millions of devices. ### Responsibilities - Design and optimize analog front-end building blocks for SerDes IP, including voltage and current-mode drivers, equalizers (CTLE, FFE, DFE), CDR circuits, PLLs, DLLs, VCOs, phase interpolators, bandgaps, and regulators - Run SPICE simulations across PVT corners and create verification test benches that validate performance against PCIe 6.0, PCIe 7.0, PAM4, Ethernet, USB, HDMI, or other high-speed protocol specifications - Collaborate closely with layout engineers to minimize parasitic resistance and capacitance, reduce mismatch, and account for proximity effects in sub-micron CMOS processes - Work with digital RTL engineers to verify calibration loops, adaptation algorithms, and control logic that tune your analog circuits in real time - Present simulation results, design tradeoffs, and performance data in peer reviews and customer-facing technical discussions - Document circuit architecture, design features, verification strategies, and test plans for integration into larger SerDes products - Own the full lifecycle of your blocks from spec to silicon, including post-layout verification, characterization support, and design-for-reliability checks for electromigration, IR drop, aging, and ESD ### The Impact You Will Have - Your circuits will enable multi-gigabit data transfer in AI accelerators, data center switches, automotive SoCs, and consumer electronics shipping in millions of units - You will help Synopsys deliver SerDes IP that meets the performance and power targets our customers depend on to win in competitive markets - Your layout optimization and simulation rigor will reduce respins, saving months of schedule and significant engineering cost - The verification strategies you define will catch corner-case failures before tapeout, improving first-pass silicon success rates - Your collaboration with digital and system teams will ensure analog-digital co-design works seamlessly, not just in theory but in real integrated test chips - You will contribute to the technical foundation of next-generation high-speed standards, influencing how the industry builds faster, more efficient links - Your documentation and knowledge sharing will raise the design quality and speed of the entire analog team ### Requirements - PhD with 2+ years of hands-on SerDes or high-speed analog design experience, or BTech/MTech with 5 to 10 years in the same domain - Silicon-proven experience designing and bringing up analog or mixed-signal blocks in production chips, you have seen your circuits work in real silicon - Deep expertise in at least several of these building blocks: analog front-end transceivers, voltage/current-mode drivers, PLLs, DLLs, VCOs, CDR circuits, bandgaps, regulators, CTLE, FFE, DFE, impedance calibrators, serializers, deserializers, or phase interpolators - Strong proficiency with SPICE simulation tools and sub-micron CMOS design methodologies, you know how to set up corners, sweep parameters, and interpret results that matter - Experience optimizing layout for performance, including parasitic extraction, device matching, stress effects, and design-for-reliability considerations like electromigration, IR drop, and aging - Familiarity with scripting languages such as TCL or Perl for automation and simulation flow setup is a strong plus - Working knowledge of high-speed serial standards like PAM4, PCIe 6.0, PCIe 7.0, Ethernet, USB, SATA, HDMI, or MIPI is highly valued ### Benefits - Comprehensive medical and healthcare plans that work for you and your family - In addition to company holidays, we have ETO and FTO Programs - Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more - Purchase Synopsys common stock at a 15% discount, with a 24-month look-back - Save for your future with our retirement plans that vary by region and country - Competitive salaries ## Skills ### Required - SerDes - analog design - SPICE simulation - CMOS design - layout optimization ### Nice to have - scripting languages - high-speed serial standards --- Source: [Apply at careers.synopsys.com](https://careers.synopsys.com/job/bengaluru/analog-design-staff-engineer/44408/97550666512?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)