# ASIC Engineering Technical Leader

**Company**: Cisco
**Location**: Bangalore, India
**Experience**: senior
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology

**Apply**: https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/Bangalore-India/ASIC-Engineer---RTL-Design--Verilog--System-Verilog---CDC--Lint---Exp---8--to-10-years---Bangalore_2030071?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/job/asic-engineering-technical-leader-0bb1b78e-761/

## Description

Join the Cisco SiliconOne team as an ASIC Engineering Technical Leader. You'll work on crafting complex chips for Enterprise and Service Provider solutions, with exposure to all aspects of systems and applications.

Your Impact: As an ASIC Engineering Technical Leader, you'll have an ASIC design background with hands-on experience in RTL design and in-depth knowledge of ASIC/SoC development cycles. Your responsibilities include:

- Architectural work: in-depth understanding of the architecture, identification of problems, and solutions

- All aspects of implementation: specification, design, timing-analysis, power-optimization, flow automation, optimization of logic for low power and area

- Document and improve standard methodologies for product success

Minimum Qualifications:

- BS/MS and 5+/3+ years respectively of hands-on experience in large-scale, high-performance ASIC

- RTL development (Verilog, SystemVerilog, VCS, Spyglass, CDC, Formal verification)

- Experienced in system debug and SW/HW bringup, system validation of silicon towards FCS

- Gate-level understanding of RTL and Synthesis

- Programming/scripting skills (C, C++, Perl)

- Hardware Emulation Platforms and tools (such as EVE, Veloce)

- Good written/verbal interpersonal skills and leadership skills

Preferred Qualifications:

- Worked in architecture and definition of high-scale, high-performance ASICs

- Validated experience in implementation: specification, RTL design, lint, cdc, timing analysis, formal verification, system testing

- Validated experience in flow automation (scripting, Makefiles, etc), and establishing guidelines for the team

- Good interpersonal skills, and validated leadership to accurately describe issues/improvements and lead team for on-time completion

Why Cisco? At Cisco, we're revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We've been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds.

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## Skills

### Required
- ASIC design
- RTL development
- Verilog
- SystemVerilog
- VCS
- Spyglass
- CDC
- Formal verification
- C
- C++
- Perl
- Hardware Emulation Platforms

### Nice to have
- architecture
- high-scale ASICs
- implementation
- flow automation
- leadership

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Source: [Apply at cisco.wd5.myworkdayjobs.com](https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/Bangalore-India/ASIC-Engineer---RTL-Design--Verilog--System-Verilog---CDC--Lint---Exp---8--to-10-years---Bangalore_2030071?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)