# Senior Physical Design and Timing Engineer

**Company**: NVIDIA
**Location**: Santa Clara, CA
**Experience**: senior
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology

**Apply**: https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-Physical-Design-and-Timing-Engineer_JR2020717?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_0b13912a-738

## Description

NVIDIA is seeking a Senior Physical Design and Timing Engineer to join its growing team. The engineer will drive physical design and timing of high-frequency and low-power NVIDIA CPUs, GPUs, LPUs, and SoCs.

**Job Overview** As a Senior Physical Design and Timing Engineer at NVIDIA, you will be responsible for driving physical design and timing of high-frequency and low-power NVIDIA CPUs, GPUs, LPUs, and SoCs at block level, cluster level, and/or full chip level. You will help drive frontend and backend implementation from RTL to gds2, including synthesis, equivalence checking, floor-planning, timing constraints, timing and power convergence, and ECO implementation. You will work in a cross-functional environment interacting with multiple teams and apply knowledge and experience to improve the convergence flows working with the Methodology Team.

**Responsibilities**

- Drive physical design and timing of high-frequency and low-power NVIDIA CPUs, GPUs, LPUs, and SoCs at block level, cluster level, and/or full chip level.

- Help drive frontend and backend implementation from RTL to gds2, including synthesis, equivalence checking, floor-planning, timing constraints, timing and power convergence, and ECO implementation.

- Work in a cross-functional environment interacting with multiple teams.

- Apply knowledge and experience to improve the convergence flows working with the Methodology Team.

**Requirements**

- BS (or equivalent experience) in Electrical or Computer Engineering with 5+ years experience or MS (or equivalent experience) with 3+ years experience in Synthesis and Timing.

- Solid experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints generation and management, and timing convergence.

- Experience in critical path planning and crafting.

- Hands-on experience in logic synthesis and equivalence checking/FV.

- Good understanding of hardware architecture and hands-on skills in RTL/logic design for timing closure.

- Expertise in physical design and optimization, such as placement, routing, cell sizing, buffering, logic restructuring.

- Understanding of DFT logic and hands-on experience in design closure.

- Expertise in analyzing and converging crosstalk delay, noise glitch, and electrical/manufacturing rules in deep-sub micron processes.

- Knowledge in process variation effect modeling and experience in design convergence taking into account variations.

- Expertise and in-depth knowledge of industry standard EDA tools.

- Proficiency in programming and scripting languages, such as Perl, Tcl, Make, Python.

**Benefits** NVIDIA offers highly competitive salaries and a comprehensive benefits package. You will also be eligible for equity and benefits.

## Skills

### Required
- Physical Design
- Timing Analysis
- Synthesis
- Static Timing Analysis (STA)
- Logic Synthesis
- Equivalence Checking
- Floor-planning
- Timing Constraints
- Power Convergence
- ECO Implementation
- DFT Logic
- Design Closure
- Crosstalk Delay
- Noise Glitch
- Electrical/Manufacturing Rules
- Process Variation Effect Modeling
- EDA Tools
- Perl
- Tcl
- Make
- Python

### Nice to have
- High-performance design
- CPU
- GPU
- LPU
- Implementation and timing convergence
- DFT timing closure
- Methodology and/or flow development/automation

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Source: [Apply at nvidia.wd5.myworkdayjobs.com](https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-Physical-Design-and-Timing-Engineer_JR2020717?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)