We are seeking a Sr. Staff ASIC Digital Design Engineer to join our LPDDR PHY IP team at Synopsys. As a leader in the mixed-signal IP market, Synopsys develops cutting-edge semiconductor solutions. In this role, you will contribute to all phases of DDR PHY IP design, from specification to productization, and provide customer support. Key responsibilities: Design and micro-architect LPDDR PHY IP, writing Verilog and SystemVerilog code and design specifications Conduct simulation and analysis of designs, collaborating with Verification, Timing, DFT, and Power teams Analyze and fix Lint, CDC/RDC, DFT, Timing, and power issues Maintain and improve design automation flow and processes Requirements: BS in Electrical Engineering Minimum 8 years of experience in complex technical development Experience with synthesizable Verilog and System Verilog design concepts, coding, and implementation Familiarity with front-end design flows, including linting, synthesis, timing investigation and closure, cross-domain clocking, DFT, and power optimization techniques Excellent communication skills and self-motivation Understanding of memory and memory PHY architecture is a plus We offer comprehensive benefits, including health and wellness programs, time away, family support, ESPP, retirement plans, and competitive salaries.