# ASIC Digital Verification Engineer

**Company**: Synopsys
**Location**: Dublin, Leinster
**Work arrangement**: onsite
**Experience**: senior
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology
**Ticker**: SNPS
**Wikidata**: https://www.wikidata.org/wiki/Q2303478

**Apply**: https://careers.synopsys.com/job/dublin/asic-digital-verification-engineer/44408/102657541664?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_0994eea7-1a5

## Description

Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

You are an ASIC verification engineer who cares as much about how verification gets done as about what gets verified. You have solid hands-on UVM experience, and when you see a repetitive or fragile step in the flow, your first instinct is to automate it. AI coding agents are already part of how you work every day: you use them to write, review, and maintain code, and you know where they help and where they need a careful human eye.

At Synopsys, you will join the R&D team developing the PCI Express (PCIe) and Compute Express Link (CXL) controller IP used in data centers, artificial intelligence, automotive, and many other applications. The verification components and flows you build will be used by the whole team, every day.

**Responsibilities**

- Design, deploy, maintain, and support reusable and configurable verification components for PCIe and CXL controller IP.

- Develop UVM testbench architecture, agents, and test sequences within your area of the verification environment.

- Build and extend AI-assisted flows for verification and automation, using coding agents such as Cursor, Claude Code, or GitHub Copilot to create, review, and maintain testbench code, scripts, and regression infrastructure.

- Integrate state-of-the-art Synopsys tools into the product workflow.

- Work with the infrastructure team to ensure fair and efficient access to shared compute and tool resources.

- Contribute to internal forums on verification methodology, automation, and AI-assisted development best practices.

- Coach more junior engineers on UVM, automation, and effective use of AI coding agents.

**The Impact You Will Have**

- Shorten verification turnaround for PCIe and CXL IP by automating repetitive and error-prone work across the flow.

- Make AI-assisted development a practical, everyday part of how the team verifies IP.

- Deliver reusable verification components that other engineers in the team build on.

- Own entire flows or processes within your area, with direct impact on the team’s delivery results.

- Improve how efficiently the team uses shared compute and tool resources.

- Help spread good practices across the team through methodology forums and day-to-day coaching.

**Requirements**

- Bachelor’s or master’s degree in Computer Engineering, Electrical Engineering, or Communication Engineering.

- 5+ years of ASIC design verification, UVM-based functional verification, or related experience (3+ years with a master’s degree).

- Solid SystemVerilog and UVM skills, including testbench architecture, agents, and test sequences.

- Hands-on experience working within AI-assisted development flows, using coding agents such as Cursor, Claude Code, or GitHub Copilot.

- Proficiency in scripting languages (Python, Tcl, Perl, Unix shell).

- Strong analytical skills and the ability to work in a dynamic, fast-paced team environment.

**Benefits**

- Comprehensive medical and healthcare plans that work for you and your family.

- In addition to company holidays, we have ETO and FTO Programs.

- Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

- Purchase Synopsys common stock at a 15% discount, with a 24-month look-back.

- Save for your future with our retirement plans that vary by region and country.

- Competitive salaries.

## Skills

### Required
- SystemVerilog
- UVM
- Python
- Tcl
- Perl
- Unix shell
- Cursor
- Claude Code
- GitHub Copilot

### Nice to have
- Software design best practices
- Experience with reusable and configurable designs
- Experience with revision control systems and development best practices
- Knowledge of the PCI Express and/or CXL protocols

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Source: [Apply at careers.synopsys.com](https://careers.synopsys.com/job/dublin/asic-digital-verification-engineer/44408/102657541664?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)