# Serdes IP Design Engineer

**Company**: Synopsys
**Location**: Wuhan, Hubei
**Experience**: mid
**Job type**: employee
**Category**: Engineering
**Industry**: Technology
**Ticker**: SNPS
**Wikidata**: https://www.wikidata.org/wiki/Q2303478

**Apply**: https://careers.synopsys.com/job/wuhan/serdes-ip-design-engineer/44408/101344394576?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_07822727-039

## Description

We are seeking a highly motivated and innovative digital design engineer with knowledge of ASIC development flow.

The successful candidate will work as part of a highly experienced mixed-signal design and verification team, targeting current and next-generation high-speed SERDES, such as USB4.0v2, USB4.0, PCIe4.0, Ethernet, DP2.0, HDMI2.1, and MIPI MPHY products (up to 40 Gbps).

Key responsibilities include:

- Designing and verifying high-speed SERDES and data recovery circuits

- Working with a professional team of digital and mixed-signal engineers to deliver high-end mixed-signal designs

- Developing and performing functional and performance tests on prototype test-chips

- Collaborating with different design groups and customer support teams

Requirements:

- MSEE graduate or BSEE plus minimum 3 years of digital design and verification experience in the industry

- Good experience in writing block-level test-cases including constrained directed random tests

- Familiarity with Verilog and VCS, and good knowledge of back-end synthesis tools DC/PT

- Knowledge of digital design methodologies, ATE production testing, DFT insertion, Synthesis constraints and flows

- Scripting experience in Shell, Perl, Python, and TCL is a plus

- Good theoretical and practical understanding of digital signal processing and data recovery circuits

- Good communication skills for interacting between different design groups and customer support teams

Preferred experience:

- RTL coding, modeling of analog blocks, and writing complex system-level test-benches in Verilog

- Defining synthesis design constraints and resolving STA issues as well as gate-level simulation failures

- Defining Clock/Reset domain crossing design constraints and evaluating violations using CDC/RDC tools

- Enhancing and maintaining existing SERDES PHY IPs supporting multiple protocols

- Interacting with Application Engineers for customer support and resolving technical issues with Analog and P&R teams.

Benefits:

- Comprehensive medical and healthcare plans

- Time away programs, including ETO and FTO

- Family support, including maternity and paternity leave, parenting resources, adoption and surrogacy assistance

- ESPP, allowing purchase of Synopsys common stock at a 15% discount

- Retirement plans that vary by region and country

- Competitive salaries

## Skills

### Required
- ASIC development flow
- digital design
- verification
- Verilog
- VCS
- DC/PT
- DFT insertion
- Synthesis constraints
- Shell scripting
- Perl scripting
- Python scripting
- TCL scripting
- digital signal processing
- data recovery circuits

### Nice to have
- RTL coding
- analog block modeling
- system-level test-benches
- STA issues resolution
- CDC/RDC tools
- SERDES PHY IPs
- customer support

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Source: [Apply at careers.synopsys.com](https://careers.synopsys.com/job/wuhan/serdes-ip-design-engineer/44408/101344394576?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)