# Senior ASIC Design Engineer - DFX

**Company**: NVIDIA
**Location**: Santa Clara, CA
**Experience**: senior
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology

**Apply**: https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-ASIC-Design-Engineer---DFX_JR2020883?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_06e874fe-b73

## Description

We are seeking a Senior ASIC Design Engineer - DFX to join our team at NVIDIA. As a key member of our DFX Methodology Team, you will play a critical role in shaping the architecture, design, implementation, and verification of DFT IPs for our next-generation SoC products.

Your key responsibilities will include:

- Owning the architecture and design of fuse controller and other DFT IPs for cutting-edge SoC designs.

- Developing, deploying, and enhancing DFT methodologies for scalability and future product needs.

- Defining and aligning feature sets by working closely with architects, platform, and software teams.

- Partnering with design, verification, synthesis, timing, and backend teams to ensure cohesive integration.

- Creating and executing test plans to support both functional and DFT full-chip verification.

- Supporting post-silicon bring-up and validation efforts including debug and issue resolution.

- Mentoring junior engineers on test design strategies and trade-offs related to cost, quality, and performance.

To be successful in this role, you will need:

- A Bachelor's degree (or equivalent experience) with 8+ years of experience, or a Master's degree in Electrical Engineering or related field with 6+ years experience.

- 5+ years of hands-on experience in SoC architecture, RTL design, and verification.

- Strong proficiency in micro-architecture and RTL development using Verilog. (UVM experience is a plus.)

- Deep expertise in DFT design, methodology, and implementation.

- Familiarity with related domains such as clocking, STA, place & route, and power optimization.

- Experience in post-silicon bring-up on ATE, including understanding of pattern formats, test program development, and failure analysis.

- Proficiency in scripting languages such as Python, Perl, or Tcl.

- Excellent communication skills and a collaborative mindset,with a curiosity and passion for solving complex technical challenges.

In return for your hard work, we offer competitive compensation, comprehensive benefits, and meaningful opportunities to advance your career.

## Skills

### Required
- SoC architecture
- RTL design
- DFT design
- Verilog
- Python
- Perl
- Tcl

### Nice to have
- UVM experience

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Source: [Apply at nvidia.wd5.myworkdayjobs.com](https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-ASIC-Design-Engineer---DFX_JR2020883?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)