# ASIC Design/Verification, Architect

**Company**: Synopsys
**Location**: Reading
**Experience**: senior
**Job type**: employee
**Category**: Engineering
**Industry**: Technology
**Ticker**: SNPS
**Wikidata**: https://www.wikidata.org/wiki/Q2303478

**Apply**: https://careers.synopsys.com/job/reading/asic-design-verification-architect/44408/94524277376?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_06c07210-350

## Description

Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

You are an experienced and highly skilled ASIC Digital Verification Engineer with a passion for ensuring the highest quality in digital design. Your expertise allows you to work independently, taking on complex challenges and delivering innovative solutions. You are detail-oriented, with a strong analytical mindset, and can communicate effectively with various stakeholders.

Responsibilities:

- Designing, implementing and optimizing verification environments to ensure the correctness of Interface IP protocols.

- Creating, executing and tracking against detailed test plans to verify complex ASIC designs.

- Developing and maintaining verification IP and testbenches using System Verilog and UVM.

- Collaborating with design and architecture teams identifying fix bugs.

- Performing functional coverage analysis and driving coverage closure.

- Mentoring and guiding junior verification engineers in best practices and methodologies.

The Impact You Will Have:

- Ensuring the delivery of high-quality, reliable ASIC designs that meet customer specifications.

- Enhancing the robustness and efficiency of our verification processes and methodologies.

- Contributing to the successful launch of Interface IP products, impacting various industries.

- Driving innovation and excellence within the verification team.

- Improving the overall performance and functionality of Synopsys' IP offerings.

- Fostering a culture of continuous improvement and technical excellence.

Requirements:

- Extensive experience in ASIC digital verification, specifically with Interface IP protocols, such as PCIe, CXL, DDR, Ethernet, AMBA (CHI, AXI, AHB, APB).

- Proficiency in System Verilog, SVA and UVM methodologies.

- Strong understanding of digital design and verification concepts.

- Familiarity with wider digital ASIC and IP development flow, including RTL design through synthesis.

- Experience with simulation tools such as VCS, Model Sim, or similar.

- Strong analytical and problem-solving skills, with the ability to tackle complex and unique design challenges.

- Excellent communication skills, with the ability to effectively collaborate with cross-functional teams and stakeholders.

Benefits:

- Comprehensive medical and healthcare plans that work for you and your family.

- Time away programs, including ETO and FTO.

- Family support, including maternity and paternity leave, parenting resources, adoption and surrogacy assistance.

- ESPP: purchase Synopsys common stock at a 15% discount, with a 24-month look-back.

- Retirement plans that vary by region and country.

- Competitive salaries.

## Skills

### Required
- ASIC digital verification
- Interface IP protocols
- System Verilog
- SVA
- UVM
- digital design
- verification concepts
- RTL design
- simulation tools

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Source: [Apply at careers.synopsys.com](https://careers.synopsys.com/job/reading/asic-design-verification-architect/44408/94524277376?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)