# Senior ASIC Design Engineer

**Company**: NVIDIA
**Location**: Santa Clara
**Work arrangement**: onsite
**Experience**: senior
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology

**Apply**: https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-ASIC-Design-Engineer_JR2014886?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_0447dca8-af1

## Description

We are looking for a Sr. ASIC Design Engineer to design and implement the world's leading SoCs and GPUs. This position offers the opportunity to have real impact in a multifaceted, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence.

**Responsibilities:**

- Document, implement, and deliver fully verified, high-performance, area and power-efficient RTL to achieve the design targets and specifications.

- Participate in the verification of the design using sophisticated verification methodologies, including defining the verification scope and supporting the development of verification infrastructure.

- Collaborate with several ASIC development teams and communicate and coordinate with members of those teams, some of whom are in remote locations.

**Requirements:**

- Bachelor's or Master's degree (or equivalent experience)

- 5+ years of relevant work experience

- Proven hardware engineering background with a concentration in VLSI and Computer Architecture

- Expertise in Verilog, System Verilog, or similar HDL

- Proficient programming in Perl/Python (or similar scripting languages)

- Experience with logic synthesis and timing analysis

- Exposure and firsthand work experience with design and verification tools (VCS or equivalent simulation tools, debug tools like Verdi, GDB)

- Experience with test bench environments for unit and system-level verification

You will also be eligible for equity and benefits.

## Skills

### Required
- Verilog
- System Verilog
- Perl
- Python
- Logic Synthesis
- Timing Analysis
- VCS
- Verdi
- GDB
- Test Bench Environments

---

Source: [Apply at nvidia.wd5.myworkdayjobs.com](https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-ASIC-Design-Engineer_JR2014886?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)