# Post-Silicon Validation, Principal Engineer **Company**: Synopsys **Location**: Hillsboro, Oregon **Experience**: senior **Job type**: full-time **Salary**: $151000-$227000 **Category**: Engineering **Industry**: Technology **Ticker**: SNPS **Wikidata**: https://www.wikidata.org/wiki/Q2303478 **Apply**: https://careers.synopsys.com/job/hillsboro/post-silicon-validation-principal-engineer/44408/101617800480?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply **Canonical**: https://yubhub.co/jobs/job_030d78b7-e1f ## Description You will join Synopsys, the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. As a Post-Silicon Validation, Principal Engineer, you will define how Synopsys validates UCIe die-to-die IP, own the silicon sign-off decision, and be the technical authority customers call when their multi-die product is stuck. You have spent a decade or more bringing silicon to life, and you know that the hardest problems do not show up in simulation. They show up in a customer's lab when the link will not train and nobody can explain why. You are the person who can connect observations across the analog, digital, protocol, package, and system domains, identify the most likely failure mechanisms, and drive the investigation to a defensible conclusion. **Responsibilities** - Define the post-silicon validation and characterization strategy for UCIe-based die-to-die interface IP, including the methodology, coverage models, and sign-off criteria that determine whether silicon is ready to ship - Act as the final technical escalation point for silicon issues where root cause is not evident from the data, requiring you to evaluate intangibles across analog circuit behavior, package and interposer channel effects, link training firmware, protocol layer state machines, and system integration constraints - Lead the bring up and debug of customer silicon, working remotely or sometimes on-site in customer labs to resolve sideband and mainband link training failures, lane repair and reversal issues, degraded mode operation, and chiplet interoperability problems - Own the architecture and technical direction of the validation software platform in Python, including lab automation frameworks, data infrastructure, measurement correlation engines, and the instrumentation the organization depends on - Establish how die-to-die links are characterized when direct probe access is limited or unavailable, defining the use of on-die instrumentation, eye margining techniques, built-in monitors, and the correlation of that data back to bench measurements and simulation results - Drive validation programs that span multiple related areas of the business, coordinating across analog design, digital design, firmware, product engineering, applications, and marketing to reach shared technical outcomes and silicon readiness milestones - Represent Synopsys in technical engagements with major customers and, where appropriate, in industry and standards forums such as the UCIe Consortium **The Impact You Will Have** - Resolve the class of silicon problems that would otherwise stall a program or delay a customer's multi-die product launch, directly affecting time-to-market and revenue outcomes - Raise the technical capability of the entire validation discipline through the methodology, tooling, and measurement standards you establish and the engineers you coach - Shape how the organization and industry approaches validation of next-generation UCIe data rates, packaging technologies, and chiplet topologies before those problems arrive, influencing roadmap and design decisions upstream - Deliver measurable impact on department targets including sign-off schedules, silicon respin avoidance, and the speed at which new IP reaches production readiness - Establish Synopsys as the credible technical partner customers turn to when their silicon does not work, strengthening customer relationships and competitive positioning - Feed silicon reality back into the design process, influencing architecture, circuit design, and packaging strategy with data that only post-silicon validation can provide **Requirements** - Bachelor's degree in Electrical Engineering or Computer Engineering with a minimum of 10 years of related experience, or an advanced degree with a minimum of 8 years of related experience - Extensive expertise in post-silicon validation, characterization, and debug of high-speed mixed-signal interface IP across multiple silicon generations and process nodes - Authoritative command of the UCIe specification, including the PHY and D2D adapter layers, link initialization and training, sideband operation, lane repair and reversal, and the tradeoffs between standard and advanced packaging; direct UCIe or other die-to-die interface experience is strongly preferred, and deep high-speed SerDes experience is applicable - Recognized depth in high-speed link analysis, including equalization, jitter decomposition, crosstalk, and package, interposer, and substrate channel behavior, grounded in signals and systems concepts and transmission line theory - Advanced software architecture capability across multiple languages including Python, with experience building large-scale lab automation frameworks, data infrastructure, and measurement correlation systems - Expert-level command of high-speed oscilloscopes, BERTs, spectrum analyzers, and network analyzers, including understanding the limits of the instruments themselves and how to validate links that cannot be directly probed - Demonstrated success leading customer silicon bring up and debug engagements, working in customer lab environments and owning the technical relationship with external engineering teams; experience with software version control systems such as GitLab and with issue and task tracking through Jira and Confluence is a plus **Benefits** We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. ## Skills ### Required - post-silicon validation - characterization - debug of high-speed mixed-signal interface IP - UCIe specification - high-speed link analysis - Python - lab automation frameworks - data infrastructure - measurement correlation systems - high-speed oscilloscopes - BERTs - spectrum analyzers - network analyzers ### Nice to have - direct UCIe or other die-to-die interface experience - deep high-speed SerDes experience - software version control systems such as GitLab - issue and task tracking through Jira and Confluence --- Source: [Apply at careers.synopsys.com](https://careers.synopsys.com/job/hillsboro/post-silicon-validation-principal-engineer/44408/101617800480?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)