# Layout Design, Sr Engineer

**Company**: Synopsys
**Location**: Yerevan
**Experience**: senior
**Category**: Engineering
**Industry**: Technology
**Ticker**: SNPS
**Wikidata**: https://www.wikidata.org/wiki/Q2303478

**Apply**: https://careers.synopsys.com/job/yerevan/layout-design-sr-engineer/44408/103122221152?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/job/layout-design-sr-engineer-00207fd7-1a2/

## Description

Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

You have spent real time in layout tools, not just opening Virtuoso but actually building memory cells, bitcells, and arrays that have to meet density, performance, and reliability targets in nodes where a few nanometers matter. You understand that SRAM layout is not just drawing rectangles, it is about symmetry, matching, minimizing parasitic capacitance, and making sure the circuit your designer spent weeks optimizing does not fall apart because of a poorly routed metal layer.

You will work on memory IP that ships in real products, and the layout decisions you make will directly affect performance, yield, and time to market.

### Responsibilities

- Design and implement full-custom layout for SRAM memory macros in advanced technology nodes, from bitcell to array to peripheral circuits

- Optimize layouts for area, performance, and power while maintaining design rule compliance and manufacturability

- Run and resolve DRC, LVS, ERC, Antenna, Density, and EM checks using Calibre, ICV, and other verification tools

- Collaborate directly with circuit designers to translate schematics into physical layouts that meet electrical and reliability specifications

- Work with process and foundry teams to interpret and apply technology files, design rules, and device models

- Iterate on layout based on parasitic extraction results and post-layout simulation feedback

### The Impact You Will Have

- Your layouts will directly determine the area efficiency, speed, and power consumption of SRAM macros used across Synopsys IP portfolios

- Optimized layout work you deliver will enable faster time to market for customers designing chips in leading-edge nodes

- Clean DRC/LVS closure you achieve will reduce tapeout delays and prevent costly respins

- Collaboration with circuit teams will improve design quality and catch issues before they reach silicon

- Your expertise in advanced nodes will help Synopsys maintain leadership in memory IP competitiveness

### Requirements

- Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or Microelectronics

- 1+ years of hands-on experience in SRAM or custom memory layout design

- Strong expertise in SRAM architecture, memory circuits, custom layout techniques, matching, symmetry, and device reliability

- Proficiency with Cadence Virtuoso, Calibre, Custom Compiler, and ICV

- Solid understanding of DRC/LVS closure, RC extraction, and EM/IR considerations

- Experience with advanced technology nodes (7nm, 5nm, or below is a plus)

### Benefits

- Comprehensive medical and healthcare plans that work for you and your family

- Time away: company holidays, ETO and FTO Programs

- Family support: maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more

- ESPP: purchase Synopsys common stock at a 15% discount, with a 24-month look-back

- Retirement plans: save for your future with our retirement plans that vary by region and country

- Competitive salaries

For more fresh new jobs, check out [yubhub.co](https://yubhub.co/).

## Skills

### Required
- Electrical Engineering
- Electronics Engineering
- Microelectronics
- SRAM architecture
- memory circuits
- custom layout techniques
- Cadence Virtuoso
- Calibre
- Custom Compiler
- ICV

### Nice to have
- advanced technology nodes (7nm, 5nm, or below)

---

Source: [Apply at careers.synopsys.com](https://careers.synopsys.com/job/yerevan/layout-design-sr-engineer/44408/103122221152?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)